DPDMA_CH0_CNTL (DPDMA) Register Description
| Register Name | DPDMA_CH0_CNTL |
|---|---|
| Offset Address | 0x0000000218 |
| Absolute Address | 0x00FD4C0218 (DPDMA) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Channel 0 Control Register |
DPDMA_CH0_CNTL (DPDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:30 | razRead as zero | 0x0 | Reserved for future use |
| DSCR_DLY_CNT | 29:20 | rwNormal read/write | 0x0 | Programmable Count used to schedule DSCR Count |
| DSCR_AXCACHE | 19:16 | rwNormal read/write | 0x0 | Descriptor fetch/update AXI CMD uses this bit to generate ARCACHE bit |
| DSCR_AXPROT | 15:14 | rwNormal read/write | 0x0 | Used for all descriptor fetch/update for channel 0, following is the how AxProt bits are generated for descriptor fetch AXPROT[0] = [14] (bit 14 of this register) AXPROT[1] = TZ_SLCR_DPDMA (security input for DPDMA) AXPROT[2] = [15] (bit 15 of this register) |
| QOS_DATA_RD | 13:10 | rwNormal read/write | 0x0 | DMA uses this QOS value along with AXI cmd for descriptor write |
| QOS_DSCR_RD | 9:6 | rwNormal read/write | 0x0 | DMA uses this QOS value along with AXI cmd for data read |
| QOS_DSCR_WR | 5:2 | rwNormal read/write | 0x0 | DMA uses this QOS value along with AXI cmd for descriptor read |
| PAUSE | 1 | rwNormal read/write | 0x0 | Pause for DMA channel, pause preserves the DMA state. It stopes generating new fetch request untill Pause is High. 1: DMA Channel is paused 0: Normar operation |
| EN | 0 | rwNormal read/write | 0x0 | Enable/Disable for DMA Channel, Trigger generated by start trigger register is only respected if DMA channel is enabled. Once DMA channel is disable, it goes to idle and can be restarted using trigger after enableing the channel 1: DMA Channel is enable 0: DMA Channel is desable |