DPDMA_CH0_DSCR_STRT_ADDRE (DPDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DPDMA_CH0_DSCR_STRT_ADDRE (DPDMA) Register Description

Register NameDPDMA_CH0_DSCR_STRT_ADDRE
Offset Address0x0000000200
Absolute Address 0x00FD4C0200 (DPDMA)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDescriptor Start Address Extension Register

DPDMA_CH0_DSCR_STRT_ADDRE (DPDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16razRead as zero0x0Reseved for future use
MSB15:0rwNormal read/write0x04 bit address the extention for first descriptor fetch