DPDMA_CH1_DSCR_STRT_ADDR (DPDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DPDMA_CH1_DSCR_STRT_ADDR (DPDMA) Register Description

Register NameDPDMA_CH1_DSCR_STRT_ADDR
Offset Address0x0000000304
Absolute Address 0x00FD4C0304 (DPDMA)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionDescriptor Start Address Register

DPDMA_CH1_DSCR_STRT_ADDR (DPDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
LSB31:0rwNormal read/write0x032 bit start address for first descriptor fetch