DPDMA_EIEN (DPDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DPDMA_EIEN (DPDMA) Register Description

Register NameDPDMA_EIEN
Offset Address0x000000001C
Absolute Address 0x00FD4C001C (DPDMA)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionInterrupt Enable Register. A write of 1 to this location will unmask the interrupt. (IMR: 0)

DPDMA_EIEN (DPDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
RD_CMD_FIFO_FULL31woWrite-only0x0Read cmd FIFO full condition is detected during data/descriptor read
DSCR_DONE_ERR530woWrite-only0x0DMA has already processed this descriptor on channel 5
- Ignore Done is not set
- Done bit is set
DSCR_DONE_ERR429woWrite-only0x0DMA has already processed this descriptor on channel 4
- Ignore Done is not set
- Done bit is set
DSCR_DONE_ERR328woWrite-only0x0DMA has already processed this descriptor on channel 3
- Ignore Done is not set
- Done bit is set
DSCR_DONE_ERR227woWrite-only0x0DMA has already processed this descriptor on channel 2
- Ignore Done is not set
- Done bit is set
DSCR_DONE_ERR126woWrite-only0x0DMA has already processed this descriptor on channel 1
- Ignore Done is not set
- Done bit is set
DSCR_DONE_ERR025woWrite-only0x0DMA has already processed this descriptor on channel 0
- Ignore Done is not set
- Done bit is set
DSCR_WR_AXI_ERR524woWrite-only0x0Error occurred during descriptor write on Channel 5
- SLAVE/DECODE Error on BRESP
DSCR_WR_AXI_ERR423woWrite-only0x0Error occurred during descriptor write on Channel 4
- SLAVE/DECODE Error on BRESP
DSCR_WR_AXI_ERR322woWrite-only0x0Error occurred during descriptor write on Channel 3
- SLAVE/DECODE Error on BRESP
DSCR_WR_AXI_ERR221woWrite-only0x0Error occurred during descriptor write on Channel 2
- SLAVE/DECODE Error on BRESP
DSCR_WR_AXI_ERR120woWrite-only0x0Error occurred during descriptor write on Channel 1
- SLAVE/DECODE Error on BRESP
DSCR_WR_AXI_ERR019woWrite-only0x0Error occurred during descriptor write on Channel 0
- SLAVE/DECODE Error on BRESP
DSCR_CRC_ERR518woWrite-only0x0Error occurred during descriptor read on Channel 5
- CRC Mismatch
DSCR_CRC_ERR417woWrite-only0x0Error occurred during descriptor read on Channel 4
- CRC Mismatch
DSCR_CRC_ERR316woWrite-only0x0Error occurred during descriptor read on Channel 3
- CRC Mismatch
DSCR_CRC_ERR215woWrite-only0x0Error occurred during descriptor read on Channel 2
- CRC Mismatch
DSCR_CRC_ERR114woWrite-only0x0Error occurred during descriptor read on Channel 1
- CRC Mismatch
DSCR_CRC_ERR013woWrite-only0x0Error occurred during descriptor read on Channel 0
- CRC Mismatch
DSCR_PRE_ERR512woWrite-only0x0Error occurred during descriptor read on Channel 5
- Preamble Mismatch
DSCR_PRE_ERR411woWrite-only0x0Error occurred during descriptor read on Channel 4
- Preamble Mismatch
DSCR_PRE_ERR310woWrite-only0x0Error occurred during descriptor read on Channel 3
- Preamble Mismatch
DSCR_PRE_ERR2 9woWrite-only0x0Error occurred during descriptor read on Channel 2
- Preamble Mismatch
DSCR_PRE_ERR1 8woWrite-only0x0Error occurred during descriptor read on Channel 1
- Preamble Mismatch
DSCR_PRE_ERR0 7woWrite-only0x0Error occurred during descriptor read on Channel 0
- Preamble Mismatch
DSCR_RD_AXI_ERR5 6woWrite-only0x0Error occurred during descriptor read on Channel 5
- SLAVE/DECODE Error on any beat of data
DSCR_RD_AXI_ERR4 5woWrite-only0x0Error occurred during descriptor read on Channel 4
- SLAVE/DECODE Error on any beat of data
DSCR_RD_AXI_ERR3 4woWrite-only0x0Error occurred during descriptor read on Channel 3
- SLAVE/DECODE Error on any beat of data
DSCR_RD_AXI_ERR2 3woWrite-only0x0Error occurred during descriptor read on Channel 2
- SLAVE/DECODE Error on any beat of data
DSCR_RD_AXI_ERR1 2woWrite-only0x0Error occurred during descriptor read on Channel 1
- SLAVE/DECODE Error on any beat of data
DSCR_RD_AXI_ERR0 1woWrite-only0x0Error occurred during descriptor read on Channel 0
- SLAVE/DECODE Error on any beat of data
INV_APB 0woWrite-only0x0see DPDMA_INT_STATUS register for details