DPDMA_EIMR (DPDMA) Register Description
| Register Name | DPDMA_EIMR |
|---|---|
| Offset Address | 0x0000000018 |
| Absolute Address | 0x00FD4C0018 (DPDMA) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0xFFFFFFFF |
| Description | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
DPDMA_EIMR (DPDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| RD_CMD_FIFO_FULL | 31 | roRead-only | 0x1 | Read cmd FIFO full condition is detected during data/descriptor read |
| DSCR_DONE_ERR5 | 30 | roRead-only | 0x1 | DMA has already processed this descriptor on channel 5 - Ignore Done is not set - Done bit is set |
| DSCR_DONE_ERR4 | 29 | roRead-only | 0x1 | DMA has already processed this descriptor on channel 4 - Ignore Done is not set - Done bit is set |
| DSCR_DONE_ERR3 | 28 | roRead-only | 0x1 | DMA has already processed this descriptor on channel 3 - Ignore Done is not set - Done bit is set |
| DSCR_DONE_ERR2 | 27 | roRead-only | 0x1 | DMA has already processed this descriptor on channel 2 - Ignore Done is not set - Done bit is set |
| DSCR_DONE_ERR1 | 26 | roRead-only | 0x1 | DMA has already processed this descriptor on channel 1 - Ignore Done is not set - Done bit is set |
| DSCR_DONE_ERR0 | 25 | roRead-only | 0x1 | DMA has already processed this descriptor on channel 0 - Ignore Done is not set - Done bit is set |
| DSCR_WR_AXI_ERR5 | 24 | roRead-only | 0x1 | Error occurred during descriptor write on Channel 5 - SLAVE/DECODE Error on BRESP |
| DSCR_WR_AXI_ERR4 | 23 | roRead-only | 0x1 | Error occurred during descriptor write on Channel 4 - SLAVE/DECODE Error on BRESP |
| DSCR_WR_AXI_ERR3 | 22 | roRead-only | 0x1 | Error occurred during descriptor write on Channel 3 - SLAVE/DECODE Error on BRESP |
| DSCR_WR_AXI_ERR2 | 21 | roRead-only | 0x1 | Error occurred during descriptor write on Channel 2 - SLAVE/DECODE Error on BRESP |
| DSCR_WR_AXI_ERR1 | 20 | roRead-only | 0x1 | Error occurred during descriptor write on Channel 1 - SLAVE/DECODE Error on BRESP |
| DSCR_WR_AXI_ERR0 | 19 | roRead-only | 0x1 | Error occurred during descriptor write on Channel 0 - SLAVE/DECODE Error on BRESP |
| DSCR_CRC_ERR5 | 18 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 5 - CRC Mismatch |
| DSCR_CRC_ERR4 | 17 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 4 - CRC Mismatch |
| DSCR_CRC_ERR3 | 16 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 3 - CRC Mismatch |
| DSCR_CRC_ERR2 | 15 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 2 - CRC Mismatch |
| DSCR_CRC_ERR1 | 14 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 1 - CRC Mismatch |
| DSCR_CRC_ERR0 | 13 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 0 - CRC Mismatch |
| DSCR_PRE_ERR5 | 12 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 5 - Preamble Mismatch |
| DSCR_PRE_ERR4 | 11 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 4 - Preamble Mismatch |
| DSCR_PRE_ERR3 | 10 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 3 - Preamble Mismatch |
| DSCR_PRE_ERR2 | 9 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 2 - Preamble Mismatch |
| DSCR_PRE_ERR1 | 8 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 1 - Preamble Mismatch |
| DSCR_PRE_ERR0 | 7 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 0 - Preamble Mismatch |
| DSCR_RD_AXI_ERR5 | 6 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 5 - SLAVE/DECODE Error on any beat of data |
| DSCR_RD_AXI_ERR4 | 5 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 4 - SLAVE/DECODE Error on any beat of data |
| DSCR_RD_AXI_ERR3 | 4 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 3 - SLAVE/DECODE Error on any beat of data |
| DSCR_RD_AXI_ERR2 | 3 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 2 - SLAVE/DECODE Error on any beat of data |
| DSCR_RD_AXI_ERR1 | 2 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 1 - SLAVE/DECODE Error on any beat of data |
| DSCR_RD_AXI_ERR0 | 1 | roRead-only | 0x1 | Error occurred during descriptor read on Channel 0 - SLAVE/DECODE Error on any beat of data |
| INV_APB | 0 | roRead-only | 0x1 | see DPDMA_INT_STATUS register for details |