DPDMA_EISR (DPDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DPDMA_EISR (DPDMA) Register Description

Register NameDPDMA_EISR
Offset Address0x0000000014
Absolute Address 0x00FD4C0014 (DPDMA)
Width32
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionInterrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.

DPDMA_EISR (DPDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
RD_CMD_FIFO_FULL31wtcReadable, write a 1 to clear0x0Read cmd FIFO full condition is detected during data/descriptor read
DSCR_DONE_ERR530wtcReadable, write a 1 to clear0x0DMA has already processed this descriptor on channel 5
- Ignore Done is not set
- Done bit is set
DSCR_DONE_ERR429wtcReadable, write a 1 to clear0x0DMA has already processed this descriptor on channel 4
- Ignore Done is not set
- Done bit is set
DSCR_DONE_ERR328wtcReadable, write a 1 to clear0x0DMA has already processed this descriptor on channel 3
- Ignore Done is not set
- Done bit is set
DSCR_DONE_ERR227wtcReadable, write a 1 to clear0x0DMA has already processed this descriptor on channel 2
- Ignore Done is not set
- Done bit is set
DSCR_DONE_ERR126wtcReadable, write a 1 to clear0x0DMA has already processed this descriptor on channel 1
- Ignore Done is not set
- Done bit is set
DSCR_DONE_ERR025wtcReadable, write a 1 to clear0x0DMA has already processed this descriptor on channel 0
- Ignore Done is not set
- Done bit is set
DSCR_WR_AXI_ERR524wtcReadable, write a 1 to clear0x0Error occurred during descriptor write on Channel 5
- SLAVE/DECODE Error on BRESP
DSCR_WR_AXI_ERR423wtcReadable, write a 1 to clear0x0Error occurred during descriptor write on Channel 4
- SLAVE/DECODE Error on BRESP
DSCR_WR_AXI_ERR322wtcReadable, write a 1 to clear0x0Error occurred during descriptor write on Channel 3
- SLAVE/DECODE Error on BRESP
DSCR_WR_AXI_ERR221wtcReadable, write a 1 to clear0x0Error occurred during descriptor write on Channel 2
- SLAVE/DECODE Error on BRESP
DSCR_WR_AXI_ERR120wtcReadable, write a 1 to clear0x0Error occurred during descriptor write on Channel 1
- SLAVE/DECODE Error on BRESP
DSCR_WR_AXI_ERR019wtcReadable, write a 1 to clear0x0Error occurred during descriptor write on Channel 0
- SLAVE/DECODE Error on BRESP
DSCR_CRC_ERR518wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 5
- CRC Mismatch
DSCR_CRC_ERR417wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 4
- CRC Mismatch
DSCR_CRC_ERR316wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 3
- CRC Mismatch
DSCR_CRC_ERR215wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 2
- CRC Mismatch
DSCR_CRC_ERR114wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 1
- CRC Mismatch
DSCR_CRC_ERR013wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 0
- CRC Mismatch
DSCR_PRE_ERR512wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 5
- Preamble Mismatch
DSCR_PRE_ERR411wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 4
- Preamble Mismatch
DSCR_PRE_ERR310wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 3
- Preamble Mismatch
DSCR_PRE_ERR2 9wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 2
- Preamble Mismatch
DSCR_PRE_ERR1 8wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 1
- Preamble Mismatch
DSCR_PRE_ERR0 7wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 0
- Preamble Mismatch
DSCR_RD_AXI_ERR5 6wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 5
- SLAVE/DECODE Error on any beat of data
DSCR_RD_AXI_ERR4 5wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 4
- SLAVE/DECODE Error on any beat of data
DSCR_RD_AXI_ERR3 4wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 3
- SLAVE/DECODE Error on any beat of data
DSCR_RD_AXI_ERR2 3wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 2
- SLAVE/DECODE Error on any beat of data
DSCR_RD_AXI_ERR1 2wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 1
- SLAVE/DECODE Error on any beat of data
DSCR_RD_AXI_ERR0 1wtcReadable, write a 1 to clear0x0Error occurred during descriptor read on Channel 0
- SLAVE/DECODE Error on any beat of data
INV_APB 0wtcReadable, write a 1 to clear0x0see DPDMA_INT_STATUS register for details