DPDMA_EISR (DPDMA) Register Description
Register Name | DPDMA_EISR |
---|---|
Offset Address | 0x0000000014 |
Absolute Address | 0x00FD4C0014 (DPDMA) |
Width | 32 |
Type | wtcReadable, write a 1 to clear |
Reset Value | 0x00000000 |
Description | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
DPDMA_EISR (DPDMA) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
RD_CMD_FIFO_FULL | 31 | wtcReadable, write a 1 to clear | 0x0 | Read cmd FIFO full condition is detected during data/descriptor read |
DSCR_DONE_ERR5 | 30 | wtcReadable, write a 1 to clear | 0x0 | DMA has already processed this descriptor on channel 5 - Ignore Done is not set - Done bit is set |
DSCR_DONE_ERR4 | 29 | wtcReadable, write a 1 to clear | 0x0 | DMA has already processed this descriptor on channel 4 - Ignore Done is not set - Done bit is set |
DSCR_DONE_ERR3 | 28 | wtcReadable, write a 1 to clear | 0x0 | DMA has already processed this descriptor on channel 3 - Ignore Done is not set - Done bit is set |
DSCR_DONE_ERR2 | 27 | wtcReadable, write a 1 to clear | 0x0 | DMA has already processed this descriptor on channel 2 - Ignore Done is not set - Done bit is set |
DSCR_DONE_ERR1 | 26 | wtcReadable, write a 1 to clear | 0x0 | DMA has already processed this descriptor on channel 1 - Ignore Done is not set - Done bit is set |
DSCR_DONE_ERR0 | 25 | wtcReadable, write a 1 to clear | 0x0 | DMA has already processed this descriptor on channel 0 - Ignore Done is not set - Done bit is set |
DSCR_WR_AXI_ERR5 | 24 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor write on Channel 5 - SLAVE/DECODE Error on BRESP |
DSCR_WR_AXI_ERR4 | 23 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor write on Channel 4 - SLAVE/DECODE Error on BRESP |
DSCR_WR_AXI_ERR3 | 22 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor write on Channel 3 - SLAVE/DECODE Error on BRESP |
DSCR_WR_AXI_ERR2 | 21 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor write on Channel 2 - SLAVE/DECODE Error on BRESP |
DSCR_WR_AXI_ERR1 | 20 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor write on Channel 1 - SLAVE/DECODE Error on BRESP |
DSCR_WR_AXI_ERR0 | 19 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor write on Channel 0 - SLAVE/DECODE Error on BRESP |
DSCR_CRC_ERR5 | 18 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 5 - CRC Mismatch |
DSCR_CRC_ERR4 | 17 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 4 - CRC Mismatch |
DSCR_CRC_ERR3 | 16 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 3 - CRC Mismatch |
DSCR_CRC_ERR2 | 15 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 2 - CRC Mismatch |
DSCR_CRC_ERR1 | 14 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 1 - CRC Mismatch |
DSCR_CRC_ERR0 | 13 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 0 - CRC Mismatch |
DSCR_PRE_ERR5 | 12 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 5 - Preamble Mismatch |
DSCR_PRE_ERR4 | 11 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 4 - Preamble Mismatch |
DSCR_PRE_ERR3 | 10 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 3 - Preamble Mismatch |
DSCR_PRE_ERR2 | 9 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 2 - Preamble Mismatch |
DSCR_PRE_ERR1 | 8 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 1 - Preamble Mismatch |
DSCR_PRE_ERR0 | 7 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 0 - Preamble Mismatch |
DSCR_RD_AXI_ERR5 | 6 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 5 - SLAVE/DECODE Error on any beat of data |
DSCR_RD_AXI_ERR4 | 5 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 4 - SLAVE/DECODE Error on any beat of data |
DSCR_RD_AXI_ERR3 | 4 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 3 - SLAVE/DECODE Error on any beat of data |
DSCR_RD_AXI_ERR2 | 3 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 2 - SLAVE/DECODE Error on any beat of data |
DSCR_RD_AXI_ERR1 | 2 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 1 - SLAVE/DECODE Error on any beat of data |
DSCR_RD_AXI_ERR0 | 1 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during descriptor read on Channel 0 - SLAVE/DECODE Error on any beat of data |
INV_APB | 0 | wtcReadable, write a 1 to clear | 0x0 | see DPDMA_INT_STATUS register for details |