DPDMA_ERR_CTRL (DPDMA) Register Description
| Register Name | DPDMA_ERR_CTRL |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address | 0x00FD4C0000 (DPDMA) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Enable/Disable a error response |
By default, invalid address requests are ignored. However, a maskable interrupt exsists. By enabling this slverr_enable invalid address requests cause a slverr to occur.
DPDMA_ERR_CTRL (DPDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | razRead as zero | 0x0 | Reserved for future use |
| APB_ERR_RES | 0 | rwNormal read/write | 0x0 | When an APB (register) access occurs to an unimplemented space (there is no register at that location), the resulting pslverr will be: 0: pslverr = 1b0 1: pslverr = 1b1 There is also a maskable interrupt , "INV_APB_INT" that could be asserted, independent of what option is selected here. |