DPDMA_GBL (DPDMA) Register Description
| Register Name | DPDMA_GBL |
|---|---|
| Offset Address | 0x0000000104 |
| Absolute Address | 0x00FD4C0104 (DPDMA) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Global control register provides control to start or redirect any channel |
DPDMA_GBL (DPDMA) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:12 | razRead as zero | 0x0 | Reseved for future use |
| RTRG_CH5 | 11 | woWrite-only | 0x0 | Software can redirect channel 5 by writing 1 to this bit. Instead of using NEXT ADDRESS at the end of FRAME, DPDMA uses start address to fetch the next descriptor if this bit is written (hardware has a internal sticky copy). This is self clearing bit. |
| RTRG_CH4 | 10 | woWrite-only | 0x0 | Software can redirect channel 4 by writing 1 to this bit. Instead of using NEXT ADDRESS at the end of FRAME, DPDMA uses start address to fetch the next descriptor if this bit is written (hardware has a internal sticky copy). This is self clearing bit. |
| RTRG_CH3 | 9 | woWrite-only | 0x0 | Software can redirect channel 3 by writing 1 to this bit. Instead of using NEXT ADDRESS at the end of FRAME, DPDMA uses start address to fetch the next descriptor if this bit is written (hardware has a internal sticky copy). This is self clearing bit. |
| RTRG_CH2 | 8 | woWrite-only | 0x0 | Software can redirect channel 2 by writing 1 to this bit. Instead of using NEXT ADDRESS at the end of FRAME, DPDMA uses start address to fetch the next descriptor if this bit is written (hardware has a internal sticky copy). This is self clearing bit. |
| RTRG_CH1 | 7 | woWrite-only | 0x0 | Software can redirect channel 1 by writing 1 to this bit. Instead of using NEXT ADDRESS at the end of FRAME, DPDMA uses start address to fetch the next descriptor if this bit is written (hardware has a internal sticky copy). This is self clearing bit. |
| RTRG_CH0 | 6 | woWrite-only | 0x0 | Software can redirect channel 0 by writing 1 to this bit. Instead of using NEXT ADDRESS at the end of FRAME, DPDMA uses start address to fetch the next descriptor if this bit is written (hardware has a internal sticky copy). This is self clearing bit. |
| TRG_CH5 | 5 | woWrite-only | 0x0 | Software can start operation on Channel 5 by writing 1 to this bit |
| TRG_CH4 | 4 | woWrite-only | 0x0 | Software can start operation on Channel 4 by writing 1 to this bit |
| TRG_CH3 | 3 | woWrite-only | 0x0 | Software can start operation on Channel 3 by writing 1 to this bit |
| TRG_CH2 | 2 | woWrite-only | 0x0 | Software can start operation on Channel 2 by writing 1 to this bit |
| TRG_CH1 | 1 | woWrite-only | 0x0 | Software can start operation on Channel 1 by writing 1 to this bit |
| TRG_CH0 | 0 | woWrite-only | 0x0 | Software can start operation on Channel 0 by writing 1 to this bit |