DPDMA_ISR (DPDMA) Register Description
Register Name | DPDMA_ISR |
---|---|
Offset Address | 0x0000000004 |
Absolute Address | 0x00FD4C0004 (DPDMA) |
Width | 32 |
Type | wtcReadable, write a 1 to clear |
Reset Value | 0x00000000 |
Description | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
DPDMA_ISR (DPDMA) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
vsync_int | 27 | wtcReadable, write a 1 to clear | 0x0 | Interrupt on Vsync |
axi_rd_4k_cross | 26 | wtcReadable, write a 1 to clear | 0x0 | AXI Read Channel burst crosses 4k boundary |
wr_data_fifo_full | 25 | wtcReadable, write a 1 to clear | 0x0 | Write data FIFO full condition is detected during descriptor update |
wr_cmd_fifo_full | 24 | wtcReadable, write a 1 to clear | 0x0 | Write cmd FIFO full condition is detected during descriptor update |
dscr_err5 | 23 | wtcReadable, write a 1 to clear | 0x0 | descriptor payload is larger than line/frame size dictated by Video timing signals on channel 5 |
dscr_err4 | 22 | wtcReadable, write a 1 to clear | 0x0 | descriptor payload is larger than line/frame size dictated by Video timing signals on channel 4 |
dscr_err3 | 21 | wtcReadable, write a 1 to clear | 0x0 | descriptor payload is larger than line/frame size dictated by Video timing signals on channel 3 |
dscr_err2 | 20 | wtcReadable, write a 1 to clear | 0x0 | descriptor payload is larger than line/frame size dictated by Video timing signals on channel 2 |
dscr_err1 | 19 | wtcReadable, write a 1 to clear | 0x0 | descriptor payload is larger than line/frame size dictated by Video timing signals on channel 1 |
dscr_err0 | 18 | wtcReadable, write a 1 to clear | 0x0 | descriptor payload is larger than line/frame size dictated by Video timing signals on channel 0 |
data_axi_err5 | 17 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during data read on Channel 5 - SLAVE/DECODE Error on any beat of data |
data_axi_err4 | 16 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during data read on Channel 4 - SLAVE/DECODE Error on any beat of data |
data_axi_err3 | 15 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during data read on Channel 3 - SLAVE/DECODE Error on any beat of data |
data_axi_err2 | 14 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during data read on Channel 2 - SLAVE/DECODE Error on any beat of data |
data_axi_err1 | 13 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during data read on Channel 1 - SLAVE/DECODE Error on any beat of data |
data_axi_err0 | 12 | wtcReadable, write a 1 to clear | 0x0 | Error occurred during data read on Channel 0 - SLAVE/DECODE Error on any beat of data |
no_ostand_tran5 | 11 | wtcReadable, write a 1 to clear | 0x0 | outstanding transaction counter reached zero during pause on channel 5 |
no_ostand_tran4 | 10 | wtcReadable, write a 1 to clear | 0x0 | outstanding transaction counter reached zero during pause on channel 4 |
no_ostand_tran3 | 9 | wtcReadable, write a 1 to clear | 0x0 | outstanding transaction counter reached zero during pause on channel 3 |
no_ostand_tran2 | 8 | wtcReadable, write a 1 to clear | 0x0 | outstanding transaction counter reached zero during pause on channel 2 |
no_ostand_tran1 | 7 | wtcReadable, write a 1 to clear | 0x0 | outstanding transaction counter reached zero during pause on channel 1 |
no_ostand_tran0 | 6 | wtcReadable, write a 1 to clear | 0x0 | outstanding transaction counter reached zero during pause on channel 0 |
dscr_done5 | 5 | wtcReadable, write a 1 to clear | 0x0 | DMA is done with current descriptor, interrupt is only generated if it is enabled in current descriptor |
dscr_done4 | 4 | wtcReadable, write a 1 to clear | 0x0 | DMA is done with current descriptor, interrupt is only generated if it is enabled in current descriptor |
dscr_done3 | 3 | wtcReadable, write a 1 to clear | 0x0 | DMA is done with current descriptor, interrupt is only generated if it is enabled in current descriptor |
dscr_done2 | 2 | wtcReadable, write a 1 to clear | 0x0 | DMA is done with current descriptor, interrupt is only generated if it is enabled in current descriptor |
dscr_done1 | 1 | wtcReadable, write a 1 to clear | 0x0 | DMA is done with current descriptor, interrupt is only generated if it is enabled in current descriptor |
dscr_done0 | 0 | wtcReadable, write a 1 to clear | 0x0 | DMA is done with current descriptor, interrupt is only generated if it is enabled in current descriptor |