DPDMA_ISR (DPDMA) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DPDMA_ISR (DPDMA) Register Description

Register NameDPDMA_ISR
Offset Address0x0000000004
Absolute Address 0x00FD4C0004 (DPDMA)
Width32
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionInterrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.

DPDMA_ISR (DPDMA) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
vsync_int27wtcReadable, write a 1 to clear0x0Interrupt on Vsync
axi_rd_4k_cross26wtcReadable, write a 1 to clear0x0AXI Read Channel burst crosses 4k boundary
wr_data_fifo_full25wtcReadable, write a 1 to clear0x0Write data FIFO full condition is detected during descriptor update
wr_cmd_fifo_full24wtcReadable, write a 1 to clear0x0Write cmd FIFO full condition is detected during descriptor update
dscr_err523wtcReadable, write a 1 to clear0x0descriptor payload is larger than line/frame size dictated by Video timing signals on channel 5
dscr_err422wtcReadable, write a 1 to clear0x0descriptor payload is larger than line/frame size dictated by Video timing signals on channel 4
dscr_err321wtcReadable, write a 1 to clear0x0descriptor payload is larger than line/frame size dictated by Video timing signals on channel 3
dscr_err220wtcReadable, write a 1 to clear0x0descriptor payload is larger than line/frame size dictated by Video timing signals on channel 2
dscr_err119wtcReadable, write a 1 to clear0x0descriptor payload is larger than line/frame size dictated by Video timing signals on channel 1
dscr_err018wtcReadable, write a 1 to clear0x0descriptor payload is larger than line/frame size dictated by Video timing signals on channel 0
data_axi_err517wtcReadable, write a 1 to clear0x0Error occurred during data read on Channel 5
- SLAVE/DECODE Error on any beat of data
data_axi_err416wtcReadable, write a 1 to clear0x0Error occurred during data read on Channel 4
- SLAVE/DECODE Error on any beat of data
data_axi_err315wtcReadable, write a 1 to clear0x0Error occurred during data read on Channel 3
- SLAVE/DECODE Error on any beat of data
data_axi_err214wtcReadable, write a 1 to clear0x0Error occurred during data read on Channel 2
- SLAVE/DECODE Error on any beat of data
data_axi_err113wtcReadable, write a 1 to clear0x0Error occurred during data read on Channel 1
- SLAVE/DECODE Error on any beat of data
data_axi_err012wtcReadable, write a 1 to clear0x0Error occurred during data read on Channel 0
- SLAVE/DECODE Error on any beat of data
no_ostand_tran511wtcReadable, write a 1 to clear0x0outstanding transaction counter reached zero during pause on channel 5
no_ostand_tran410wtcReadable, write a 1 to clear0x0outstanding transaction counter reached zero during pause on channel 4
no_ostand_tran3 9wtcReadable, write a 1 to clear0x0outstanding transaction counter reached zero during pause on channel 3
no_ostand_tran2 8wtcReadable, write a 1 to clear0x0outstanding transaction counter reached zero during pause on channel 2
no_ostand_tran1 7wtcReadable, write a 1 to clear0x0outstanding transaction counter reached zero during pause on channel 1
no_ostand_tran0 6wtcReadable, write a 1 to clear0x0outstanding transaction counter reached zero during pause on channel 0
dscr_done5 5wtcReadable, write a 1 to clear0x0DMA is done with current descriptor, interrupt is only generated if it is enabled in current descriptor
dscr_done4 4wtcReadable, write a 1 to clear0x0DMA is done with current descriptor, interrupt is only generated if it is enabled in current descriptor
dscr_done3 3wtcReadable, write a 1 to clear0x0DMA is done with current descriptor, interrupt is only generated if it is enabled in current descriptor
dscr_done2 2wtcReadable, write a 1 to clear0x0DMA is done with current descriptor, interrupt is only generated if it is enabled in current descriptor
dscr_done1 1wtcReadable, write a 1 to clear0x0DMA is done with current descriptor, interrupt is only generated if it is enabled in current descriptor
dscr_done0 0wtcReadable, write a 1 to clear0x0DMA is done with current descriptor, interrupt is only generated if it is enabled in current descriptor