DPLL_TO_LPD_CTRL (CRF_APB) Register Description
| Register Name | DPLL_TO_LPD_CTRL |
|---|---|
| Offset Address | 0x000000004C |
| Absolute Address | 0x00FD1A004C (CRF_APB) |
| Width | 16 |
| Type | rwNormal read/write |
| Reset Value | 0x00000400 |
| Description | DPLL to LPD Clock Divisor. |
Program divisor for DPLL clock source (in FPD) driven to LPD clock generators. Refer to data sheet for frequency limits.
DPLL_TO_LPD_CTRL (CRF_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| DIVISOR0 | 13:8 | rwNormal read/write | 0x4 | 6-bit divider. |