DP_AUX_CLOCK_DIVIDER (DISPLAY_PORT) Register Description
| Register Name | DP_AUX_CLOCK_DIVIDER |
|---|---|
| Offset Address | 0x000000010C |
| Absolute Address | 0x00FD4A010C (DISPLAY_PORT) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | . Contains the clock divider value for generating the internal 1MHz clock from the APB host interface clock. The clock divider register provides integer division only and does not support fractional APB clock rates (for example, set to 75 for a 75 MHz APB clock). |
DP_AUX_CLOCK_DIVIDER (DISPLAY_PORT) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:16 | razRead as zero | 0x0 | |
| AUX_SIGNAL_WIDTH_FILTER | 15:8 | rwNormal read/write | 0x0 | The number of APB clocks equivalent to the recommended width of AUX pulse. Allowable values include: 8,16,24,32,40 and 48. From DP Protocol spec, AUX Pulse Width range = 0.4 to 0.6 us For example, for AXI Lite clock of 50MHz (=20ns), the filter width, when set to 24, falls in the allowable range as defined by the protocol spec. ((20*24 = 480) = 0.48us which is in the range 0.4 to 0.6us) Program a value of 24 in this register. |
| CLK_DIV | 7:0 | rwNormal read/write | 0x0 | Clock divider value. |