DP_AUX_COMMAND_REGISTER (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DP_AUX_COMMAND_REGISTER (DISPLAY_PORT) Register Description

Register NameDP_AUX_COMMAND_REGISTER
Offset Address0x0000000100
Absolute Address 0x00FD4A0100 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDP_AUX_COMMAND_REGISTER

DP_AUX_COMMAND_REGISTER (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:13razRead as zero0x0
ADDR_TRANSFER_EN12rwNormal read/write0x0When this bit is set to 1, the source will initiate Address only transfers (STOP will be sent after the command).
AUD_CH_COMMAND11:8rwNormal read/write0x0o 0x8 = AUX Write
o 0x9 = AUX Read
o 0x0 = IC Write
o 0x4 = IC Write MOT
o 0x1 = IC Read
o 0x5 = IC Read MOT
o 0x2 = IC Write Status
Reserved 7:4razRead as zero0x0
NUM_OF_BYTES 3:0rwNormal read/write0x0Specifies the number of bytes to transfer with the current command. The range of the register is 0 to 15 indicating between 1 and 16 bytes of data.