DP_AUX_REPLY_COUNT (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DP_AUX_REPLY_COUNT (DISPLAY_PORT) Register Description

Register NameDP_AUX_REPLY_COUNT
Offset Address0x000000013C
Absolute Address 0x00FD4A013C (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionProvides an internal counter of the number of AUX reply transactions received on the AUX Channel. Writing to this register clears the count.

DP_AUX_REPLY_COUNT (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8razRead as zero0x0
AUX_REPLY_COUNT 7:0clronwrReadable, clears value on write0x0[7:0] - Current reply count.