DP_AUX_REPLY_COUNT (DISPLAY_PORT) Register Description
Register Name | DP_AUX_REPLY_COUNT |
---|---|
Offset Address | 0x000000013C |
Absolute Address | 0x00FD4A013C (DISPLAY_PORT) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Provides an internal counter of the number of AUX reply transactions received on the AUX Channel. Writing to this register clears the count. |
DP_AUX_REPLY_COUNT (DISPLAY_PORT) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:8 | razRead as zero | 0x0 | |
AUX_REPLY_COUNT | 7:0 | clronwrReadable, clears value on write | 0x0 | [7:0] - Current reply count. |