DP_COMP_PATTERN_80BIT_2 (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DP_COMP_PATTERN_80BIT_2 (DISPLAY_PORT) Register Description

Register NameDP_COMP_PATTERN_80BIT_2
Offset Address0x0000000024
Absolute Address 0x00FD4A0024 (DISPLAY_PORT)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionDescription same as DP_COMP_PATTERN_80BIT_1 (0x20)

DP_COMP_PATTERN_80BIT_2 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
BITS_63_3231:0rwNormal read/write0x0Bits [63:32]