DP_COMP_PATTERN_80BIT_3 (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DP_COMP_PATTERN_80BIT_3 (DISPLAY_PORT) Register Description

Register NameDP_COMP_PATTERN_80BIT_3
Offset Address0x0000000028
Absolute Address 0x00FD4A0028 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionDescription same as DP_COMP_PATTERN_80BIT_1 (0x20)

DP_COMP_PATTERN_80BIT_3 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16razRead as zero0x0
BITS_79_6415:0rwNormal read/write0x0Bits [79:64] of 80bit custom pattern