DP_FORCE_SCRAMBLER_RESET (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DP_FORCE_SCRAMBLER_RESET (DISPLAY_PORT) Register Description

Register NameDP_FORCE_SCRAMBLER_RESET
Offset Address0x00000000C0
Absolute Address 0x00FD4A00C0 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionReads from this register always return 0x0.

DP_FORCE_SCRAMBLER_RESET (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1razRead as zero0x0
FORCE_SCR_RESET 0woWrite-only0x01 forces a scrambler reset.