| Field Name | Bits | Type | Reset Value | Description |
|---|
| VSYNC_TS | 31 | wtcReadable, write a 1 to clear | 0x0 | A 1 indicates that VSYNC Timestamp is available. This is generated on every VSYNC event. The TS itself is stored in AV_BUFFER_STC_VIDEO_VSYNC_TS_REG0 and REG1 registers |
| EXT_VSYNC_TS | 30 | wtcReadable, write a 1 to clear | 0x0 | A 1 indicates that External VSYNC has triggered Timestamp. This is generated on every posedge of external VSYNC signal. The TS itself is stored in AV_BUFFER_STC_EXT_VSYNC_TS_REG0 and REG1 registers |
| CUST_TS | 29 | wtcReadable, write a 1 to clear | 0x0 | A 1 indicates that a user defined Custom event has triggered Timestamp. The TS itself is stored in AV_BUFFER_STC_CUSTOM_EVENT_TS_REG0 and REG1 registers |
| CUST_TS_2 | 28 | wtcReadable, write a 1 to clear | 0x0 | A 1 indicates that a user defined Custom event 2 has triggered Timestamp. The TS itself is stored in AV_BUFFER_STC_CUSTOM_EVENT2_TS_REG0 and REG1 registers |
| CHBUF0_OVERFLW | 27 | wtcReadable, write a 1 to clear | 0x0 | AV Buffer manager channel buffer 0 overflow |
| CHBUF1_OVERFLW | 26 | wtcReadable, write a 1 to clear | 0x0 | AV Buffer manager channel buffer 1 overflow |
| CHBUF2_OVERFLW | 25 | wtcReadable, write a 1 to clear | 0x0 | AV Buffer manager channel buffer 2 overflow |
| CHBUF3_OVERFLW | 24 | wtcReadable, write a 1 to clear | 0x0 | AV Buffer manager channel buffer 3 overflow |
| CHBUF4_OVERFLW | 23 | wtcReadable, write a 1 to clear | 0x0 | AV Buffer manager channel buffer 4 overflow |
| CHBUF5_OVERFLW | 22 | wtcReadable, write a 1 to clear | 0x0 | AV Buffer manager channel buffer 5 overflow |
| CHBUF0_UNDERFLW | 21 | wtcReadable, write a 1 to clear | 0x0 | AV Buffer manager channel buffer 0 underflow |
| CHBUF1_UNDERFLW | 20 | wtcReadable, write a 1 to clear | 0x0 | AV Buffer manager channel buffer 1 underflow |
| CHBUF2_UNDERFLW | 19 | wtcReadable, write a 1 to clear | 0x0 | AV Buffer manager channel buffer 2 underflow |
| CHBUF3_UNDERFLW | 18 | wtcReadable, write a 1 to clear | 0x0 | AV Buffer manager channel buffer 3 underflow |
| CHBUF4_UNDERFLW | 17 | wtcReadable, write a 1 to clear | 0x0 | AV Buffer manager channel buffer 4 underflow |
| CHBUF5_UNDERFLW | 16 | wtcReadable, write a 1 to clear | 0x0 | AV Buffer manager channel buffer 5 underflow |
| PIXEL0_MATCH | 15 | wtcReadable, write a 1 to clear | 0x0 | When VCOUNT and HCOUNT programmed in B074 matches early VCOUNT |
| PIXEL1_MATCH | 14 | wtcReadable, write a 1 to clear | 0x0 | When VCOUNT and HCOUNT programmed in B078 matches early VCOUNT |
| VBLNK_START | 13 | wtcReadable, write a 1 to clear | 0x0 | Interrupt at start of early Vertical blanking |
| LIV_ABUF_UNDRFLW | 12 | wtcReadable, write a 1 to clear | 0x0 | Interrupt asserted when live audio is enabled at subsystem, but the input from PL is not matching audio sample rate. |
| Reserved | 11:6 | razRead as zero | 0x0 | |
| EXT_PKT_TXD | 5 | wtcReadable, write a 1 to clear | 0x0 | Extended packet is transmitted and controller is ready to accept new packet. |
| HPD_PULSE_DET | 4 | wtcReadable, write a 1 to clear | 0x0 | A pulse on the HPD line was detected. The duration of the pulse can be determined by reading 0x150. |
| REPLY_TIMEOUT | 3 | wtcReadable, write a 1 to clear | 0x0 | A reply timeout has occurred. |
| REPLY_RECEIVED | 2 | wtcReadable, write a 1 to clear | 0x0 | An AUX reply transaction has been detected. |
| HPD_EVENT | 1 | wtcReadable, write a 1 to clear | 0x0 | This interrupt is asserted after the detection of HPD(previously DISCONNECTED) or after loss of HPD(previously connected and went LOW for 2ms or more). |
| HPD_IRQ | 0 | wtcReadable, write a 1 to clear | 0x0 | An interrupt is with proper timing is received on HPD |