DP_LINK_BW_SET (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DP_LINK_BW_SET (DISPLAY_PORT) Register Description

Register NameDP_LINK_BW_SET
Offset Address0x0000000000
Absolute Address 0x00FD4A0000 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionSets the value of the main link bandwidth for the sink device.

DP_LINK_BW_SET (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8razRead as zero0x0
BW 7:0rwNormal read/write0x0Sets the value of the main link bandwidth for the sink device.
o 0x06 = 1.62 Gbps
o 0x0A = 2.7 Gbps
o 0x14 = 5.4 Gbps