DP_LINK_QUAL_PATTERN_SET (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DP_LINK_QUAL_PATTERN_SET (DISPLAY_PORT) Register Description

Register NameDP_LINK_QUAL_PATTERN_SET
Offset Address0x0000000010
Absolute Address 0x00FD4A0010 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionTo transmit the link quality pattern

DP_LINK_QUAL_PATTERN_SET (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:3razRead as zero0x0
EXT 2rwNormal read/write0x0This bit is used along with LINK_QUAL_PAT_SET. Set this bit to 1 to transmit HBR2 Compliance pattern(when LINK_QUAL_PAT_SET = 2b01)
or 80-bit custom pattern(when LINK_QUAL_PAT_SET = 2b00).
LNK_QUAL_PAT_SET 1:0rwNormal read/write0x0Transmit the link quality pattern.
- [1:0] - Enable transmission of the link quality test patterns.
o 00 = Link quality test pattern not transmitted
o 01 = D10.2 test pattern (unscrambled) transmitted(Reserved. This feature can be enabled using TP1 selection)
o 10 = Symbol Error Rate measurement pattern
o 11 = PRBS7 transmitted (Reserved. This feature can be enabled using PRBS7 transmit feature
Reg 0x230)