DP_MAIN_STREAM_MISC0 (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DP_MAIN_STREAM_MISC0 (DISPLAY_PORT) Register Description

Register NameDP_MAIN_STREAM_MISC0
Offset Address0x00000001A4
Absolute Address 0x00FD4A01A4 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionMiscellaneous stream attributes.Implements the attribute information contained in the DisplayPort MISC0 register described in section 2.2.4 of the standard.

DP_MAIN_STREAM_MISC0 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8razRead as zero0x0
BPC 7:5rwNormal read/write0x0Bit depth per color/component.
YCBCR_COLR 4rwNormal read/write0x0YCbCr Colorimetry.
DYNC_RANGE 3rwNormal read/write0x0Dynamic Range.
COMP_FORMAT 2:1rwNormal read/write0x0Component Format.
SYNC_CLOCK 0rwNormal read/write0x0Synchronous Clock