DP_MAIN_STREAM_M_VID (DISPLAY_PORT) Register Description
| Register Name | DP_MAIN_STREAM_M_VID |
|---|---|
| Offset Address | 0x00000001AC |
| Absolute Address | 0x00FD4A01AC (DISPLAY_PORT) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | M value for the video stream as computed by the source core. If synchronous clocking mode is used, this register must be written with the M value. |
DP_MAIN_STREAM_M_VID (DISPLAY_PORT) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:24 | razRead as zero | 0x0 | |
| M_VID | 23:0 | rwNormal read/write | 0x0 | Unsigned value computed in the asynchronous clock mode. |