DP_MAIN_STREAM_VSTART (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DP_MAIN_STREAM_VSTART (DISPLAY_PORT) Register Description

Register NameDP_MAIN_STREAM_VSTART
Offset Address0x00000001A0
Absolute Address 0x00FD4A01A0 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionNumber of lines between the leading edge of the vertical sync and the first line of active data.

DP_MAIN_STREAM_VSTART (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16razRead as zero0x0
VSTART15:0rwNormal read/write0x0Vertical start line count.