DP_MSA_TRANSFER_UNIT_SIZE (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DP_MSA_TRANSFER_UNIT_SIZE (DISPLAY_PORT) Register Description

Register NameDP_MSA_TRANSFER_UNIT_SIZE
Offset Address0x00000001B0
Absolute Address 0x00FD4A01B0 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000040
DescriptionSets the size of a transfer unit in the framing logic On reset, transfer size is set to 64.

DP_MSA_TRANSFER_UNIT_SIZE (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:7razRead as zero0x0
TU_SIZE 6:0rwNormal read/write0x40This number should be in the range of 32 to 64 and is set to a fixed value that depends on the inbound video mode. Note that bit 0 cannot be written (the transfer unit size is always even).