DP_PHY_CLOCK_SELECT (DISPLAY_PORT) Register Description
| Register Name | DP_PHY_CLOCK_SELECT |
|---|---|
| Offset Address | 0x0000000234 |
| Absolute Address | 0x00FD4A0234 (DISPLAY_PORT) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Instructs the PHY PLL to generate the proper clock frequency for the required link rate |
DP_PHY_CLOCK_SELECT (DISPLAY_PORT) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:8 | razRead as zero | 0x0 | |
| Reserved | 7:3 | rwNormal read/write | 0x0 | |
| SEL | 2:0 | rwNormal read/write | 0x0 | o 0x05 = 5.40 Gb/s link o 0x03 = 2.70 Gb/s link o 0x01 = 1.62 Gb/s link |