DP_PHY_PRECURSOR_LANE_0 (DISPLAY_PORT) Register Description
| Register Name | DP_PHY_PRECURSOR_LANE_0 |
|---|---|
| Offset Address | 0x000000024C |
| Absolute Address | 0x00FD4A024C (DISPLAY_PORT) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Set the pre-cursor level(post cursor 1for cadence GT) for lane 0 of the DisplayPort link |
DP_PHY_PRECURSOR_LANE_0 (DISPLAY_PORT) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:5 | razRead as zero | 0x0 | |
| PRECURSOR0 | 4:0 | rwNormal read/write | 0x0 | Controls the pre-cursor level for lane 0 of the transmitter. The mapping of the four levels supported by the DisplayPort standard to the 32 levels indicated here is implementation specific |