DP_PHY_PRECURSOR_LANE_1 (DISPLAY_PORT) Register Description
| Register Name | DP_PHY_PRECURSOR_LANE_1 |
|---|---|
| Offset Address | 0x0000000250 |
| Absolute Address | 0x00FD4A0250 (DISPLAY_PORT) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Set the pre-cursor level(post cursor 1 for Cadence GT) for lane 1 of the DisplayPort link |
DP_PHY_PRECURSOR_LANE_1 (DISPLAY_PORT) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:5 | razRead as zero | 0x0 | |
| PRECURSOR1 | 4:0 | rwNormal read/write | 0x0 | Bit definition identical to that of PHY_PRECURSOR_LANE_0. |