DP_PHY_RESET (DISPLAY_PORT) Register Description
| Register Name | DP_PHY_RESET |
|---|---|
| Offset Address | 0x0000000200 |
| Absolute Address | 0x00FD4A0200 (DISPLAY_PORT) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00010002 |
| Description | Reset the transmitter PHY. |
DP_PHY_RESET (DISPLAY_PORT) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:17 | razRead as zero | 0x0 | |
| EN_8B_10B | 16 | rwNormal read/write | 0x1 | Enable/Disable 8B/10B encoding from GT |
| Reserved | 15:2 | razRead as zero | 0x0 | |
| GT_RESET | 1 | rwNormal read/write | 0x1 | Set to 1 to hold the GT in reset. Clear to release. |