DP_PHY_STATUS (DISPLAY_PORT) Register Description
| Register Name | DP_PHY_STATUS |
|---|---|
| Offset Address | 0x0000000280 |
| Absolute Address | 0x00FD4A0280 (DISPLAY_PORT) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Provides the current status from the PHY. |
DP_PHY_STATUS (DISPLAY_PORT) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:8 | razRead as zero | 0x0 | |
| Reserved | 5 | roRead-only | 0x0 | |
| PLL_LOCKED | 4 | roRead-only | 0x0 | GT PLL locked status |
| RATE_CHANGE_DONE_0_1 | 3:2 | roRead-only | 0x0 | Received PHYSTATUS pulse from GT after rate change request from lanes 0(bit2) and 1(bit3) |
| RESET_LANES_0_1 | 1:0 | roRead-only | 0x0 | Reset done for lanes 0 and 1. |