| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:12 | razRead as zero | 0x0 | |
| AUX_REPLY_STATE | 11:4 | roRead-only | 0x1 | Internal AUX reply state machine status bits. |
| REPLY_ERROR | 3 | roRead-only | 0x0 | When set to a 1, the AUX reply logic has detected an error in the reply to the most recent AUX transaction. |
| REQUEST_IN_PROGRESS | 2 | roRead-only | 0x0 | - [2] - REQUEST_IN_PROGRESS: The AUX transaction request controller sets this bit to a 1 while actively transmitting a request on the AUX serial bus. The bit is set to 0 when the AUX transaction request controller is idle. |
| REPLY_IN_PROGRESS | 1 | roRead-only | 0x0 | The AUX reply detection logic sets this bit to a 1 while receiving a reply on the AUX serial bus. The bit is 0 otherwise. |
| REPLY_RECEIVED | 0 | roRead-only | 0x0 | This bit is set to 0 when the AUX request controller begins sending bits on the AUX serial bus. The AUX reply controller sets this bit to 1 when a complete and valid reply transaction has been received |