DP_TRAINING_PATTERN_SET (DISPLAY_PORT) Register Description
| Register Name | DP_TRAINING_PATTERN_SET |
|---|---|
| Offset Address | 0x000000000C |
| Absolute Address | 0x00FD4A000C (DISPLAY_PORT) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | To force training pattern |
DP_TRAINING_PATTERN_SET (DISPLAY_PORT) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:2 | razRead as zero | 0x0 | |
| TP_SET | 1:0 | rwNormal read/write | 0x0 | Sets the link training mode. [1:0] - Set the link training pattern according to the two bit code. o 00 = Training off o 01 = Training pattern 1, used for clock recovery o 10 = Training pattern 2, used for channel equalization o 11 = Training pattern 3, used for channel equalization for cores with DisplayPort v1.2. |