DP_TRANSMIT_PRBS7 (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DP_TRANSMIT_PRBS7 (DISPLAY_PORT) Register Description

Register NameDP_TRANSMIT_PRBS7
Offset Address0x0000000230
Absolute Address 0x00FD4A0230 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionEnable the pseudo random bit sequence 7 pattern transmission for link quality assessment. PRBS is generated by the DP transmit controller only. PRBS feature of Cadence GT is unused

DP_TRANSMIT_PRBS7 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1razRead as zero0x0
TX_PRBS7 0rwNormal read/write0x0A1 in this bit enables the transmission of the sequence.