DP_TX_M_AUD (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DP_TX_M_AUD (DISPLAY_PORT) Register Description

Register NameDP_TX_M_AUD
Offset Address0x0000000328
Absolute Address 0x00FD4A0328 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionM value of audio stream as computed by transmitter

DP_TX_M_AUD (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:24razRead as zero0x0
MAUD23:0rwNormal read/write0x0Unsigned value computed when audio clock and link clock are synchronous.