DP_TX_PHY_POWER_DOWN (DISPLAY_PORT) Register Description
| Register Name | DP_TX_PHY_POWER_DOWN |
|---|---|
| Offset Address | 0x0000000238 |
| Absolute Address | 0x00FD4A0238 (DISPLAY_PORT) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Control PHY Power down |
DP_TX_PHY_POWER_DOWN (DISPLAY_PORT) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:4 | razRead as zero | 0x0 | |
| POWER_DWN | 3:0 | rwNormal read/write | 0x0 | Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - lane 1 |