DP_TX_USER_FIFO_OVERFLOW (DISPLAY_PORT) Register Description
| Register Name | DP_TX_USER_FIFO_OVERFLOW |
|---|---|
| Offset Address | 0x0000000110 |
| Absolute Address | 0x00FD4A0110 (DISPLAY_PORT) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | . Indicates an overflow in the user FIFO. The event may occur if the video rate does not match the TU size programming. |
DP_TX_USER_FIFO_OVERFLOW (DISPLAY_PORT) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | razRead as zero | 0x0 | |
| OVERFLOW | 0 | clronrdReadable, clears value on read | 0x0 | : A 1 indicates that the internal FIFO has detected an overflow condition. This bit clears upon read. |