DP_USER_DATA_COUNT_PER_LANE (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DP_USER_DATA_COUNT_PER_LANE (DISPLAY_PORT) Register Description

Register NameDP_USER_DATA_COUNT_PER_LANE
Offset Address0x00000001BC
Absolute Address 0x00FD4A01BC (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionThis register is used to translate the number of pixels per line to the native internal 16-bit datapath.

DP_USER_DATA_COUNT_PER_LANE (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:18razRead as zero0x0
DATA_CNT_PER_LANE17:0rwNormal read/write0x0If (HRES * bits per pixel) is divisible by 16, then
word_per_line = ((HRES * bits per pixel)/16)
Else
word_per_line = (INT((HRES * bits per pixel)/16))+1
For single-lane design:
Set USER_DATA_COUNT_PER_LANE = words_per_line - 1
For 2-lane design:
If words_per_line is divisible by 2, then
Set USER_DATA_COUNT_PER_LANE = words_per_line - 2
Else
Set USER_DATA_COUNT_PER_LANE = words_per_line + MOD(words_per_line,2) - 2