DP_VIDEO_REF_CTRL (CRF_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DP_VIDEO_REF_CTRL (CRF_APB) Register Description

Register NameDP_VIDEO_REF_CTRL
Offset Address0x0000000070
Absolute Address 0x00FD1A0070 (CRF_APB)
Width32
TyperwNormal read/write
Reset Value0x00000002
DescriptionDisplayPort Video Clock Generator Control.

DP_VIDEO_REF_CTRL (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CLKACT24rwNormal read/write0x0Clock active control.
0: disable. Clock stop.
1: enable.
DIVISOR121:16rwNormal read/write0x06-bit divider.
DIVISOR013:8rwNormal read/write0x06-bit divider.
SRCSEL 2:0rwNormal read/write0x2Clock generator input source.
000: VPLL
010: DPLL
011: RPLL_TO_FPD