DQMAP0 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DQMAP0 (DDRC) Register Description

Register NameDQMAP0
Offset Address0x0000000280
Absolute Address 0x00FD070280 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionDQ Map Register 0

This register is static. Static registers can only be written when the controller is in reset.

DQMAP0 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
dq_nibble_map_12_1531:24rwNormal read/write0x0DDR4 DQ nibble map for DQ bits [12-15]
dq_nibble_map_8_1123:16rwNormal read/write0x0DDR4 DQ nibble map for DQ bits [8-11]
dq_nibble_map_4_715:8rwNormal read/write0x0DDR4 DQ nibble map for DQ bits [4-7]
dq_nibble_map_0_3 7:0rwNormal read/write0x0DDR4 DQ nibble map for DQ bits [0-3]