DQMAP2 (DDRC) Register Description
| Register Name | DQMAP2 |
|---|
| Offset Address | 0x0000000288 |
|---|
| Absolute Address |
0x00FD070288 (DDRC)
|
|---|
| Width | 32 |
|---|
| Type | rwNormal read/write |
|---|
| Reset Value | 0x00000000 |
|---|
| Description | DQ Map Register 2 |
|---|
This register is static. Static registers can only be written when the controller is in reset.
DQMAP2 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| dq_nibble_map_44_47 | 31:24 | rwNormal read/write | 0x0 | DDR4 DQ nibble map for DQ bits [44-47] |
| dq_nibble_map_40_43 | 23:16 | rwNormal read/write | 0x0 | DDR4 DQ nibble map for DQ bits [40-43] |
| dq_nibble_map_36_39 | 15:8 | rwNormal read/write | 0x0 | DDR4 DQ nibble map for DQ bits [36-39] |
| dq_nibble_map_32_35 | 7:0 | rwNormal read/write | 0x0 | DDR4 DQ nibble map for DQ bits [32-35] |