DQMAP5 (DDRC) Register Description
| Register Name | DQMAP5 |
|---|---|
| Offset Address | 0x0000000294 |
| Absolute Address | 0x00FD070294 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | DQ Map Register 5 |
This register is static. Static registers can only be written when the controller is in reset.
DQMAP5 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| dis_dq_rank_swap | 0 | rwNormal read/write | 0x0 | In DDR4 designs, all even ranks have the same DQ mapping controlled by DQMAP0-4 register as rank 0. This register provides DQ swap function for all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping |