DQSDR0 (DDR_PHY) Register Description
| Register Name | DQSDR0 |
|---|---|
| Offset Address | 0x0000000250 |
| Absolute Address | 0x00FD080250 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00088000 |
| Description | DQS Drift Register 0 |
DQSDR0 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| DFTDLY | 31:28 | rwNormal read/write | 0x0 | Number of delay taps by which the DQS gate LCDL will be updated when DQS drift is detected. Valid values are: 4b0000 = DQS gate status sampling window (DTCR1. RDLVLGDIFF) divided by 2 4b0001 = DQS gate status sampling window (DTCR1. RDLVLGDIFF) 4b0010 = 2 LCDL tap delays 4b0011 = 3 LCDL tap delays 4b0100 = 4 LCDL tap delays 4b0101 = 5 LCDL tap delays 4b0110 = 6 LCDL tap delays 4b0111 = 7 LCDL tap delays 4b1000 = 8 LCDL tap delays 4b1001 = 9 LCDL tap delays 4b1010 = 10 LCDL tap delays 4b1011 = 11 LCDL tap delays 4b1100 = 12 LCDL tap delays 4b1101 = 13 LCDL tap delays 4b1110 = 14 LCDL tap delays 4b1111 = 15 LCDL tap delays |
| DFTZQUP | 27 | rwNormal read/write | 0x0 | Drift Impedance Update: Specifies if set that the PUB should also update the I/O impedance whenever it requests and get granted the DFI bus from the controller for DQS drift updates. This feature is not supported in this revision of the PUB. |
| DFTDDLUP | 26 | rwNormal read/write | 0x0 | Drift DDL Update: Specifies if set that the PUB should also update DDLs whenever it requests and get granted the DFI bus from the controller for DQS drift updates. This feature is not supported in this revision of the PUB. |
| Reserved | 25:22 | roRead-only | 0x0 | Return zeroes on reads. |
| DFTRDSPC | 21:20 | rwNormal read/write | 0x0 | Drift Read Spacing Specifies by how much the reads that are generated by the PUB for drift compensation should be spaced from each when either DQSDR0.DFTIDLRD or DQSDR0.DFTB2BRD is set to a value greater than 1. Valid values are: 2b00 = Space out the reads by 1 CTL clock cycle (not supported) 2b01 = Wait for the data of the read to come back before sending the next read 2b10 - 2b11 = Reserved |
| DFTB2BRD | 19:16 | rwNormal read/write | 0x8 | Drift Back-to-Back Reads: Specifies the number of reads that the PUB should generate when it is configured to break long continuous back-to-back reads from the controller to allow it to sense drift. This is useful if the PUB is configured not to detect drift on every cycle, i.e. when DFTGPULSE is set to 4'b000. |
| DFTIDLRD | 15:12 | rwNormal read/write | 0x8 | Drift Idle Reads: Specifies the number of reads that the PUB should generate when it is configured to issue periodic reads when there have been no reads from the controller for a programmable number of clock cycles. Valid values are 1 (4'b0001) to 15 (4'b1111). |
| Reserved | 11:8 | roRead-only | 0x0 | Return zeroes on reads. |
| DFTGPULSE | 7:4 | rwNormal read/write | 0x0 | Gate Pulse Enable: Specifies the DDR clocks when the qs_gate signal is 1b0 when the gate is supposed to be open. Valid values are: 4b0000 = The qs_gate signal is always 1b0 when gate is open. This means that the PUB can only detect drift at the beginning of a back- to-back burst. 4b0001 - 4b1111 = Reserved |
| DFTUPMODE | 3:2 | rwNormal read/write | 0x0 | DQS Drift Update Mode: Specifies the DQSupdate mode to use: 00 = Update drift dynamically without using the DFI interface. (not supported) 01 = Update drift using the DFI PHY-initiated update protocol. 10 = RESERVED 11 = RESERVED |
| DFTDTMODE | 1 | rwNormal read/write | 0x0 | DQS Drift Detection Mode: Specifies the DQS detection mode to use: 0 = Detects drift by sampling DQS with DQS gate 1 = Detects drift by sampling DQS gate with DQS (not supported) |
| DFTDTEN | 0 | rwNormal read/write | 0x0 | DQS Drift Detection Enable: Indicates when set that the DQS drift monitoring and delay update logic is active. 0 = Drift detection and compensation is off. 1 = Drift detection and compensation is on |