DQSDR2 (DDR_PHY) Register Description
| Register Name | DQSDR2 |
|---|---|
| Offset Address | 0x0000000258 |
| Absolute Address | 0x00FD080258 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | DQS Drift Register 2 |
DQSDR2 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:24 | roRead-only | 0x0 | Return zeroes on reads. |
| DFTTHRSH | 23:16 | rwNormal read/write | 0x0 | Drift Threshold: Specifies the minimum number of DQS drift detections in one direction in order to declare it as a valid DQS drift. Any drift in the opposite direction before hitting this threshold will reset the detection counter. |
| DFTMNTPRD | 15:0 | rwNormal read/write | 0x0 | Drift Monitor Period: Specifies the minimum number of clock cycles between two drift monitor events. This field controls how often the drift status from the DATX8 is sampled by the PUB and used to compensate the drift. Note that this field only controls the minimum period of drift monitoring/compensation. The maximum period will depend on how often the reads are sent to the DRAM using either the controller or the PUB (using the DQSDR0.DFTIDLRD or DQSDR0.DFTB2BRD fields). All values are valid and indicate that drift should be monitored every (DFTMNTPRD+1) CTL clocks. |