DRAMTMG0 (DDRC) Register Description
| Register Name | DRAMTMG0 |
|---|---|
| Offset Address | 0x0000000100 |
| Absolute Address | 0x00FD070100 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x0F101B0F |
| Description | SDRAM Timing Register 0 |
All register fields are quasi-dynamic group 2 and group 4, unless described otherwise in the register field description. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.
DRAMTMG0 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| wr2pre | 30:24 | rwNormal read/write | 0xF | Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR3/LPDDR4 for this parameter. For 1T mode, divide the above value by 2. No rounding up. For 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. Programming Mode: Quasi-dynamic Group 1, Group 2, and Group 4 |
| t_faw | 21:16 | rwNormal read/write | 0x10 | tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles. Program this to (tFAW/2) and round up to next integer value. In a 4-bank design, set this register to 0x1. Unit: Clocks |
| t_ras_max | 14:8 | rwNormal read/write | 0x1B | tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. Program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of 1024 clocks. |
| t_ras_min | 5:0 | rwNormal read/write | 0xF | tRAS(min): Minimum time between activate and precharge to the same bank. For 1T mode, program this to tRAS(min)/2. No rounding up. For 2T mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks |