DRAMTMG11_SHADOW (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DRAMTMG11_SHADOW (DDRC) Register Description

Register NameDRAMTMG11_SHADOW
Offset Address0x000000212C
Absolute Address 0x00FD07212C (DDRC)
Width32
TyperwNormal read/write
Reset Value0x440C021C
DescriptionSDRAM Timing Shadow Register 11

This register is quasi-dynamic group 2 and group 4. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.

DRAMTMG11_SHADOW (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
post_mpsm_gap_x3230:24rwNormal read/write0x44DDR4: tXMPDLL:
This is the minimum Exit MPSM to commands requiring a locked DLL.
Program this to (tXMPDLL/2) and round it up to the next integer value.
Unit: Multiples of 32 clocks.
t_mpx_lh20:16rwNormal read/write0xCDDR4: tMPX_LH:
This is the minimum CS_n Low hold time to CKE rising edge.
Program this to RoundUp(tMPX_LH/2)+1.
Unit: clocks.
t_mpx_s 9:8rwNormal read/write0x2DDR4: tMPX_S:
Minimum time CS setup time to CKE.
Program this to (tMPX_S/2) and round it up to the next integer value.
Unit: Clocks.
t_ckmpe 4:0rwNormal read/write0x1CDDR4: tCKMPE: Minimum valid clock requirement after MPSM entry.
Unit: Clocks.
Divide the value calculated using the above equation by 2, and round it up to next integer.