DRAMTMG12_SHADOW (DDRC) Register Description
| Register Name | DRAMTMG12_SHADOW |
|---|---|
| Offset Address | 0x0000002130 |
| Absolute Address | 0x00FD072130 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00020610 |
| Description | SDRAM Timing Shadow Register 12 |
This register is quasi-dynamic group 2 and group 4. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.
DRAMTMG12_SHADOW (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| t_cmdcke | 17:16 | rwNormal read/write | 0x2 | tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE Program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value. |
| t_ckehcmd | 11:8 | rwNormal read/write | 0x6 | tCKEHCMD: Valid command requirement after CKE input HIGH. Program this to (tCKEHCMD/2) and round it up to next integer value. |
| t_mrd_pda | 4:0 | rwNormal read/write | 0x10 | tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. Program this to (tMRD_PDA/2) and round it up to next integer value. |