DRAMTMG13_SHADOW (DDRC) Register Description
| Register Name | DRAMTMG13_SHADOW |
|---|---|
| Offset Address | 0x0000002134 |
| Absolute Address | 0x00FD072134 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x1C200004 |
| Description | SDRAM Timing Shadow Register 13 |
This register is quasi-dynamic group 2 and group 4. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.
DRAMTMG13_SHADOW (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| odtloff | 30:24 | rwNormal read/write | 0x1C | LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. Program this to (tODTLoff/2) and round it up to next integer value. Unit: Clocks. |
| t_ccd_mw | 21:16 | rwNormal read/write | 0x20 | LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. Program this to (tCCDMW/2) and round it up to next integer value. Unit: Clocks. |
| t_ppd | 2:0 | rwNormal read/write | 0x4 | LPDDR4: tPPD: This is the minimum time from precharge to precharge command. Program this to (tPPD/2) and round it up to next integer value. Unit: Clocks. |