DRAMTMG1_SHADOW (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DRAMTMG1_SHADOW (DDRC) Register Description

Register NameDRAMTMG1_SHADOW
Offset Address0x0000002104
Absolute Address 0x00FD072104 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00080414
DescriptionSDRAM Timing Shadow Register 1

All register fields are quasi-dynamic group 2 and group 4, unless described otherwise in the register field description. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.

DRAMTMG1_SHADOW (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
t_xp20:16rwNormal read/write0x8tXP: Minimum time after power-down exit to any operation.
For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12].
If C/A parity for DDR4 is used, set to (tXP+PL) instead.
Program this to (tXP/2) and round it up to the next integer value.
Units: Clocks
rd2pre12:8rwNormal read/write0x4tRTP:
Minimum time from read to precharge of same bank.
- DDR3: tAL + max (tRTP, 4)
- DDR4: Max of following two equations:
tAL + max (tRTP, 4) or,
RL + BL/2 - tRP.
- LPDDR3: BL/2 +
max(tRTP,4) - 4
- LPDDR4: BL/2 + max(tRTP,8) - 8
For 1T mode, divide the above value by 2. No rounding up.
For 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
Unit: Clocks.
Programming Mode: Quasi-dynamic Group 1, Group 2, and Group 4
t_rc 6:0rwNormal read/write0x14tRC:
Minimum time between activates to same bank.
Program this to (tRC/2) and round up to next integer value.
Unit: Clocks.