DRAMTMG2_SHADOW (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DRAMTMG2_SHADOW (DDRC) Register Description

Register NameDRAMTMG2_SHADOW
Offset Address0x0000002108
Absolute Address 0x00FD072108 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x0305060D
DescriptionSDRAM Timing Shadow Register 2

This register is quasi-dynamic group 1, group 2, and group 4. Group 1 registers can be written when no read/write traffic is present at the DFI. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.

DRAMTMG2_SHADOW (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
write_latency29:24rwNormal read/write0x3Set to WL
Time from write command to write data on SDRAM interface. This must be set to WL.
Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the extra cycle of latency through the RDIMM
Divide the value calculated using the above equation by 2, and round it up to next integer.
This register field is not required for DDR3, as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols
Unit: clocks
read_latency21:16rwNormal read/write0x5Set to RL
Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM
Divide the value calculated using the above equation by 2, and round it up to next integer.
This register field is not required for DDR3, as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols
Unit: clocks
rd2wr13:8rwNormal read/write0x6DDR3: RL + BL/2 + 2 - WL
DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL
LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL
LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL
LPDDR4(DQ ODT is Enabled): RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK)
Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints.
Unit: Clocks.
Where:
- WL = write latency
- BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM
- RL = read latency = CAS latency
- WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4.
- RD_POSTAMBLE = read postamble. This is unique to LPDDR4.
For LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used.
Divide the value calculated using the above equation by 2, and round it up to next integer.
wr2rd 5:0rwNormal read/write0xDDDR4: CWL + PL + BL/2 + tWTR_L
Others: CWL + BL/2 + tWTR
In DDR4, minimum time from write command to read command for same bank group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints.
Unit: Clocks.
Where:
- CWL = CAS write latency
- PL = Parity latency
- BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM
- tWTR_L = internal write to read command delay for same bank group. This comes directly from the SDRAM specification.
- tWTR = internal write to read command delay. This comes directly from the SDRAM specification.
Add one extra cycle for LPDDR3/LPDDR4 operation.
Divide the value calculated using the above equation by 2, and round it up to next integer.