DRAMTMG3_SHADOW (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DRAMTMG3_SHADOW (DDRC) Register Description

Register NameDRAMTMG3_SHADOW
Offset Address0x000000210C
Absolute Address 0x00FD07210C (DDRC)
Width32
TyperwNormal read/write
Reset Value0x0050400C
DescriptionSDRAM Timing Shadow Register 3

This register is quasi-dynamic group 2 and group 4. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.

DRAMTMG3_SHADOW (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
t_mrw29:20rwNormal read/write0x5LPDDR3/LPDDR4: Time to wait after a mode register write or read (MRW or MRR).
LPDDR3 typically requires value of 10.
LPDDR4: Set this to the larger of tMRW and tMRWCKEL.
For
this register is used for the time from a MRW/MRR to all other commands.
For LDPDR3, this register is used for the time from a MRW/MRR to a MRW/MRR.
t_mrd17:12rwNormal read/write0x4tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents:
DDR3/4: Time from MRS to MRS command
LPDDR3/4: Time from MRS to non-MRS command
Program this to (tMRD/2) and round it up to the next integer value.
If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
t_mod 9:0rwNormal read/write0xCtMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command.
If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead.
Set to tMOD/2 (rounded up to next integer). Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.