DRAMTMG4 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

DRAMTMG4 (DDRC) Register Description

Register NameDRAMTMG4
Offset Address0x0000000110
Absolute Address 0x00FD070110 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x05040405
DescriptionSDRAM Timing Register 4

All register fields are quasi-dynamic group 2 and group 4, unless described otherwise in the register field description. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.

DRAMTMG4 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
t_rcd28:24rwNormal read/write0x5tRCD - tAL: Minimum time from activate to read or write command to same bank.
Program this to ((tRCD - tAL)/2) and round it up to the next integer value.
Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2.
Unit: Clocks.
Programming Mode: Quasi-dynamic Group 1, Group 2, and Group 4
t_ccd19:16rwNormal read/write0x4DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group.
Others: tCCD: This is the minimum time between two reads or two writes.
Program this to (tCCD_L/2 or tCCD/2) and round it up to the next integer value.
Unit: clocks.
t_rrd11:8rwNormal read/write0x4DDR4: tRRD_L: Minimum time between activates from bank a to bank b for same bank group.
Others: tRRD: Minimum time between activates from bank a to bank b
Program this to (tRRD_L/2 or tRRD/2) and round it up to the next integer value.
Unit: Clocks.
t_rp 4:0rwNormal read/write0x5tRP:
Minimum time from precharge to activate of same bank.
t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1.
For LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2).
Unit: Clocks.