DRAMTMG4 (DDRC) Register Description
Register Name | DRAMTMG4 |
---|---|
Offset Address | 0x0000000110 |
Absolute Address | 0x00FD070110 (DDRC) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x05040405 |
Description | SDRAM Timing Register 4 |
All register fields are quasi-dynamic group 2 and group 4, unless described otherwise in the register field description. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.
DRAMTMG4 (DDRC) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
t_rcd | 28:24 | rwNormal read/write | 0x5 | tRCD - tAL: Minimum time from activate to read or write command to same bank. Program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2. Unit: Clocks. Programming Mode: Quasi-dynamic Group 1, Group 2, and Group 4 |
t_ccd | 19:16 | rwNormal read/write | 0x4 | DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. Program this to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. Unit: clocks. |
t_rrd | 11:8 | rwNormal read/write | 0x4 | DDR4: tRRD_L: Minimum time between activates from bank a to bank b for same bank group. Others: tRRD: Minimum time between activates from bank a to bank b Program this to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Unit: Clocks. |
t_rp | 4:0 | rwNormal read/write | 0x5 | tRP: Minimum time from precharge to activate of same bank. t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. |