DRAMTMG6_SHADOW (DDRC) Register Description
| Register Name | DRAMTMG6_SHADOW |
|---|---|
| Offset Address | 0x0000002118 |
| Absolute Address | 0x00FD072118 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x02020005 |
| Description | SDRAM Timing Shadow Register 6 |
This register is quasi-dynamic group 2 and group 4. Group 2 registers can be written in self-refresh, deep power-down, and maximum power saving modes. Group 4 registers can be written depending on MSTR.frequency_mode.
DRAMTMG6_SHADOW (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| t_ckdpde | 27:24 | rwNormal read/write | 0x2 | LPDDR3: This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - LPDDR3: 2 Program this to recommended value divided by two and round it up to next integer. |
| t_ckdpdx | 19:16 | rwNormal read/write | 0x2 | This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - LPDDR3: 2 Program this to recommended value divided by two and round it up to next integer. |
| t_ckcsx | 3:0 | rwNormal read/write | 0x5 | LPDDR3/LPDDR4: This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 Program this to recommended value divided by two and round it up to next integer. |